Zero ASIC

Zero ASIC Corporation, formerly Adapteva, Inc., is a fabless semiconductor company focusing on low power many core microprocessor design.

[1][2] Adapteva was founded in 2008 with the goal of bringing a ten times advancement in floating-point performance per watt for the mobile device market.

The initial prototypes enabled Adapteva to secure US$1.5 million in series-A funding from BittWare, a company from Concord, New Hampshire, in October 2009.

Epiphany's RISC processors use a custom instruction set architecture (ISA) optimised for single-precision floating-point,[4] but are programmable in high level ANSI C using a standard GNU-GCC tool chain.

Code (possibly duplicated in each core) and stack space should be in that local memory; in addition (most) temporary data should fit there for full speed.

The design allows the programmer to leverage greater foreknowledge of independent data access patterns to avoid the runtime cost of figuring this out.

[12] The US$750,000 funding goal was reached in a month, with a minimum contribution of US$99 entitling backers to obtain one device; although the initial deadline was set for May 2013, the first single-board computers with 16-core Epiphany chip were finally shipped in December 2013.

[20] By 2016, the firm had taped out a 1024-core 64-bit variant of their Epiphany architecture that featured: larger local stores (64 KB), 64-bit addressing, double-precision floating-point arithmetic or SIMD single-precision, and 64-bit integer instructions, implemented in the 16 nm process node.