Active-pixel sensor
Noble in 1968, where each pixel sensor unit cell has a photodetector (typically a pinned photodiode) and one or more active transistors.
[5][6] An issue with CCD technology was its need for nearly perfect charge transfer in read out, which, "makes their radiation [tolerance?]
Pike and G. Sadasiv in 1969 proposed a solid-state image sensor with scanning circuits using thin-film transistors (TFTs), with photoconductive film used for the photodetector.
[7][8] A low-resolution "mostly digital" N-channel MOSFET (NMOS) imager with intra-pixel amplification, for an optical mouse application, was demonstrated by Richard F. Lyon in 1981.
[citation needed] A key element of the modern CMOS sensor is the pinned photodiode (PPD).
[1] This was the basis for the PPS,[2] which had image sensor elements with in-pixel selection transistors, proposed by Peter J.W.
[citation needed] The MOS passive-pixel sensor used just a simple switch in the pixel to read out the photodiode integrated charge.
[citation needed] Early (1960s–1970s) photodiode arrays with selection transistors within each pixel, along with on-chip multiplexer circuits, were impractically large.
It was not possible to fabricate active-pixel sensors with a practical pixel size in the 1970s, due to limited microlithography technology at the time.
[18] The CMD imager had a vertical APS structure, which increases fill-factor (or reduces pixel size) by storing the signal charge under an output NMOS transistor.
Between 1988 and 1991, Toshiba developed the "double-gate floating surface transistor" sensor, which had a lateral APS structure, with each pixel containing a buried-channel MOS photogate and a PMOS output amplifier.
[2] In 1999, Hyundai Electronics announced the commercial production of a 800x600 color CMOS image sensor based on 4T pixel with a high performance pinned photodiode with integrated ADCs and fabricated in a baseline 0.5um DRAM process.
[21] The CMOS sensor with PPD technology was further advanced and refined by R. M. Guidash in 1997, K. Yonemoto and H. Sumi in 2000, and I. Inoue in 2003.
In the QIS, the goal is to count every photon that strikes the image sensor, and to provide resolution of less than 1 million to 1 billion or more specialized photoelements (called jots) per sensor, and to read out jot bit planes hundreds or thousands of times per second resulting in terabits/sec of data.
He also patented the first CMOS image sensor for inter-oral dental X-rays with clipped corners for better patient comfort.
(see below) HV-CMOS devices are a specialty case of ordinary CMOS sensors used in high-voltage applications (for detection of high energy particles) like CERN Large Hadron Collider where a high-breakdown voltage up to ~30-120V is necessary.
[28] HV-CMOS are typically implemented by ~10 μm deep n-doped depletion zone (n-well) of a transistor on a p-type wafer substrate.
They have also been used in other fields including digital radiography, military ultra high speed image acquisition, security cameras, and optical mice.
CMOS-type APS sensors are typically suited to applications in which packaging, power management, and on-chip processing are important.
[32] The active circuitry in CMOS pixels takes some area on the surface which is not light-sensitive, reducing the photon-detection efficiency of the device (microlenses and back-illuminated sensors can mitigate this problem).
But the frame-transfer CCD also has about half the non-sensitive area for the frame store nodes, so the relative advantages depend on which types of sensors are being compared.
The use of intrapixel charge transfer can offer lower noise by enabling the use of correlated double sampling (CDS).
When the reset transistor is turned on, the photodiode is effectively connected to the power supply, VRST, clearing all integrated charge.
The read-out transistor, Msf, acts as a buffer (specifically, a source follower), an amplifier which allows the pixel voltage to be observed without removing the accumulated charge.
The select transistor, Msel, allows a single row of the pixel array to be read by the read-out electronics.
In order to increase the pixel densities, shared-row, four-ways and eight-ways shared read out, and other architectures can be employed.
High transistor count hurts fill factor, that is, the percentage of the pixel area that is sensitive to light.
Another way to achieve hard reset, with the n-type FET, is to lower the voltage of VRST relative to the on-voltage of RST.
This reduction may reduce headroom, or full-well charge capacity, but does not affect fill factor, unless VDD is then routed on a separate wire with its original voltage.
[35] Pseudo-flash reset requires separating VRST from VDD, while the other two techniques add more complicated column circuitry.
