Cray X1

The X1 shares the multistreaming processors, vector caches, and CMOS design of the SV1, the highly scalable distributed memory design of the T3E, and the high memory bandwidth and liquid cooling of the T90.

The X1 uses a 1.2 ns (800 MHz) clock cycle, and eight-wide vector pipes in MSP mode, offering a peak speed of 12.8 gigaflops per processor.

Liquid-cooled systems scale to a theoretical maximum of 4096 processors, comprising 1024 shared-memory nodes connected in a two-dimensional torus network, in 32 frames.

This upgrade almost triples the peak performance per board, but reduces the per-processor memory and interconnect bandwidth.

The X1 is notable for its development being partly funded by United States Government's National Security Agency (under the code name