Depletion-load NMOS logic
Depletion-mode n-type MOSFETs as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices.
[2] The original two types of MOSFET logic gates, PMOS and NMOS, were developed by Frosch and Derick in 1957 at Bell Labs.
The first IBM NMOS product was a memory chip with 1 kb data and 50–100 ns access time, which entered large-scale manufacturing in the early 1970s.
MOS ICs were considered interesting but inadequate for supplanting the fast bipolar circuits in anything but niche markets, such as low power applications.
One of the reasons for the low speed was that MOS transistors had gates made of aluminum which led to considerable parasitic capacitances using the manufacturing processes of the time.
The introduction of transistors with gates of polycrystalline silicon (that became the de facto standard from the mid-1970s to early 2000s) was an important first step in order to reduce this handicap.
The same year, Faggin also built the first IC using the new transistor type, the Fairchild 3708 (8-bit analog multiplexer with decoder), which demonstrated a substantially improved performance over its metal-gate counterpart.
In less than 10 years, the silicon gate MOS transistor replaced bipolar circuits as the main vehicle for complex digital ICs.
Hewlett-Packard then started to develop NMOS IC technology to get the promising speed and easy interfacing for its calculator business.
[10] Tom Haswell at HP eventually solved many problems by using purer raw materials (especially aluminum for interconnects) and by adding a bias voltage to make the gate threshold large enough; this back-gate bias remained a de facto standard solution to (mainly) sodium contaminants in the gates until the development of ion implantation (see below).
Motorola eventually served as a second source for these products and so became one of the first commercial semiconductor vendors to master the NMOS process, thanks to Hewlett-Packard.
A while later, the startup company Intel announced a 1-kbit pMOS DRAM, called 1102, developed as a custom product for Honeywell (an attempt to replace magnetic core memory in their mainframe computers).
Since the current in a device connected that way goes as the square of the voltage across the load, it provides poor pullup speed relative to its power consumption when pulled down.
[13] Mostek had the ion implantation equipment needed to create a doping profile more precise than possible with diffusion methods, so that the threshold voltage of the load transistors could be adjusted reliably.
One example of this is the NMOS 8255 PIO design, originally intended as an 8085 peripheral chip, that has been used in Z80 and x86 embedded systems and many other contexts for several decades.
According to Intel, HMOS II (1979) provided twice the density and four times the speed/power product over other typical contemporary depletion-load NMOS processes.
Today, most digital circuits, including the ubiquitous 7400 series, are manufactured using various CMOS processes with a range of different topologies employed.
Because the strength of a depletion-mode transistor falls off less on the approach to 1, they may reach 1 faster despite starting slower, i.e. conducting less current at the beginning of the transition and at steady state.
