Fin field-effect transistor

These devices have been given the generic name "FinFETs" because the source/drain region forms fins on the silicon surface.

The FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal–oxide–semiconductor) technology.

[4] The concept of a double-gate thin-film transistor (TFT) was proposed by H. R. Farrah (Bendix Corporation) and R. F. Steinberg in 1967.

[5] A double-gate MOSFET was later proposed by Toshihiro Sekigawa of the Electrotechnical Laboratory (ETL) in a 1980 patent describing the planar XMOS transistor.

They demonstrated that short-channel effects can be significantly reduced by sandwiching a fully depleted silicon-on-insulator (SOI) device between two gate electrodes connected together.

[21] In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on gate-all-around (GAA) FinFET technology.

They demonstrated dynamic random-access memory (DRAM) manufactured with a 90 nm Bulk FinFET process.

[35] FD-SOI (Fully Depleted Silicon On Insulator) has been seen as a potential low cost alternative to FinFETs.

[1] In 2013, SK Hynix began mass-production of 16 nm NAND flash memory,[30] and Samsung Electronics began production of 10 nm multi-level cell (MLC) NAND flash memory.