High-κ dielectric
The implementation of high-κ gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components, colloquially referred to as extending Moore's Law.
As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability.
Ignoring quantum mechanical and depletion effects from the Si substrate and gate, the capacitance C of this parallel plate capacitor is given by where Since leakage limitation constrains further reduction of t, an alternative method to increase gate capacitance is to alter κ by replacing silicon dioxide with a high-κ material.
As a consequence, development efforts have focused on finding a material with a requisitely high dielectric constant that can be easily integrated into a manufacturing process.
Other key considerations include band alignment to silicon (which may alter leakage current), film morphology, thermal stability, maintenance of a high mobility of charge carriers in the channel and minimization of electrical defects in the film/interface.
In 2000, Gurtej Singh Sandhu and Trung T. Doan of Micron Technology initiated the development of atomic layer deposition high-κ films for DRAM memory devices.
[5][6] In early 2007, Intel announced the deployment of hafnium-based high-κ dielectrics in conjunction with a metallic gate for components built on 45 nanometer technologies, and has shipped it in the 2007 processor series codenamed Penryn.
