Its processor, the 150 MHz HARP-1E based on the PA-RISC 1.1 architecture, solved the cache miss penalty by pseudo vector processing (PVP).
In PVP, data was loaded by prefetching to a special register bank, bypassing the cache.
Up to 2048 RISC processors could be connected via a high-speed three-dimensional crossbar network, which was able to transfer data at 300 MB/s over each link.
An upgrade to a 2048-node system, which reached a peak speed of 614 GFLOPS, was completed at the end of September 1996.
The 1024 processor system of the SR2201 achieved 220.4 GFLOPS on the LINPACK benchmark, which corresponded to 72% of the peak performance.