IBM Power microprocessors
They have also been used in data storage devices and workstations by IBM and by other server manufacturers like Bull and Hitachi.
When the telephone switch project was canceled, IBM retained the design for the general purpose processor and named it 801 after building #801 at Thomas J. Watson Research Center.
At the time of its introduction in 1996, the P2SC was the largest processor with the highest transistor count in the industry and was a leader in floating point operations.
In 2002, IBM also made a cost- and feature-reduced version of the POWER4 called PowerPC 970 by Apple's request.
It was designed for multiprocessing on a massive scale and came in multi-chip modules with onboard large L3 cache chips.
A joint organization was founded in 2004 called Power.org with the mission to unify and coordinate future development of the PowerPC specifications.
By then, the PowerPC specification was fragmented since Freescale (née Motorola) and IBM had taken different paths in their respective development of it.
The new instruction set architecture was called Power ISA and merged the PowerPC v.2.02 from the POWER5 with the PowerPC Book E specification from Freescale as well as some related technologies like the Vector-Media Extensions known under the brand name AltiVec (also called VMX by IBM) and hardware virtualization.
Older POWER and PowerPC specifications did not make the cut and those instruction sets were henceforth deprecated for good.
POWER6 was the fruit of the ambitious eCLipz Project, joining the I (AS/400), P (RS/6000) and Z (Mainframe) instruction sets under one common platform.
[3] Because of eCLipz, the POWER6 is an unusual design as it aimed for very high frequencies and sacrificed out-of-order execution, something that has been a feature for POWER and PowerPC processors since their inception.
The eight-core chip could execute 32 threads in parallel, and has a mode in which it could disable cores to reach higher frequencies for the ones that are left.
It uses a new high-performance floating point unit called VSX that merges the functionality of the traditional FPU with AltiVec.
The CAPI bus can be used to attach dedicated off-chip accelerator chips such as GPUs, ASICs and FPGAs.
[4][5][6] In December 2012, IBM began submitting patches to the 3.8 version of the Linux kernel, to support new POWER8 features including the VSX-2 instructions.
[9][10] The United States Department of Energy together with Oak Ridge National Laboratory and Lawrence Livermore National Laboratory contracted IBM and Nvidia to build two supercomputers, the Sierra and the Summit, based on POWER9 processors coupled with Nvidia's Volta GPUs.
Possibly there will be more versions in the future since the POWER9 architecture is open for licensing and modification by the OpenPOWER Foundation members.
