Layout Versus Schematic

The layout versus schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.

However, it does not guarantee if it really represents the circuit you desire to fabricate.

[1] These early programs operated mainly on the level of graph isomorphism, checking whether the schematic and layout were indeed identical.

With the advent of digital logic, this was too restrictive, since exactly the same function can be implemented in many different (and non-isomorphic) ways.

[2] LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, as well as the connections between them.