MIPS architecture processors
The R2000 also had support for up to four co-processors, one of which was built into the main central processing unit (CPU) and handled exceptions, traps and memory management, while the other three were left for other uses.
Toshiba's R3900 was a virtually first system on a chip (SoC) for the early handheld PCs that ran Windows CE.
The R4000 series, released in 1991, extended MIPS to a full 64-bit word design, moved the FPU onto the main die to form a single-chip microprocessor, and had a then high clock rate of 100 MHz at introduction.
MIPS, now a division of Silicon Graphics (SGI) named MTI, designed the low-cost R4200, the basis for the even cheaper R4300i.
QED later designed the RM7000 and RM9000 family of devices for embedded system markets like computer networking and laser printers.
QED was acquired by the semiconductor manufacturer PMC-Sierra in August 2000, the latter company continuing to invest in the MIPS architecture.
The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache.
This processor was a single-chip design, ran at a higher clock frequency than the R8000, and had larger 32 KB primary instruction and data caches.
Even with one memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.
Other members of the MIPS family include the R6000, an emitter-coupled logic (ECL) implementation produced by Bipolar Integrated Technology.
In 1981, John L. Hennessy began the Microprocessor without Interlocked Pipeline Stages (MIPS) project at Stanford University to investigate reduced instruction set computer (RISC) technology.
The results of his research convinced him of the future commercial potential of the technology, and in 1984, he took a sabbatical to found MIPS Computer Systems.
The SGI commercial designs deviated from Stanford MIPS by implementing most of the interlocks in hardware, supplying full multiply and divide instructions (among others).
This proved fairly successful due to the simplicity of the core, which allowed it to have many uses that would have formerly used much less able complex instruction set computer (CISC) designs of similar gate count and price; the two are strongly related: the price of a CPU is generally related to the number of gates and the number of external pins.
Nippon Electric Corporation (NEC), Toshiba, and SiByte (later acquired by Broadcom) each obtained licenses for the MIPS64 as soon as it was announced.
Raza Microelectronics, Inc. bought the product line from failing SandCraft and later produced devices that contained eight cores for the telecommunication and networking markets.
This was encouraged by the support of the first two versions of Microsoft's Windows NT for Alpha, MIPS and PowerPC, and to a lesser extent the Clipper architecture and SPARC.
However, as Intel quickly released faster versions of their Pentium class CPUs, Microsoft Windows NT v4.0 dropped support for anything but IA-32 and Alpha.
With SGI's decision to transition to the Itanium and IA-32 architectures in 2007 (following a 2006 Chapter 11 bankruptcy[5]) and 2009 acquisition by Rackable Systems, Inc., support ended for the MIPS/IRIX consumer market in December, 2013 as originally scheduled.
The introduction of the integrated R10000 allowed SGI to produce a system, the Origin 2000, eventually scalable to 1024 CPUs using its NUMAlink cc-NUMA interconnect.
Its MIPS-based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's Itanium IA-64 architecture.
[citation needed] The most innovative aspect of the system was its multicore processing node which integrates six MIPS64 cores, a crossbar switch memory controller, interconnect direct memory access (DMA) engine, Gigabit Ethernet and PCI Express controllers all on a single chip which consumes only 10 watts of power, yet has a peak floating point performance of 6 gigaFLOPS.
The most powerful configuration, the SC5832, is a single cabinet supercomputer consisting of 972 such node chips for a total of 5832 MIPS64 processor cores and 8.2 teraFLOPS of peak performance.
Loongson is a family of MIPS-compatible microprocessors designed by the Chinese Academy of Sciences' Institute of Computing Technology (ICT).
Independently designed by the Chinese, early models lacked support for four instructions that had been patented by MIPS Technologies.
microAptiv[12] is a compact, real-time embedded processor core with a five-stage pipeline and the microMIPS code compression instruction set.
The CPU integrates DSP and SIMD functionality to address signal processing requirements for entry-level embedded segments including industrial control, smart meters, automotive and wired/wireless communications.
