Phase-locked loop range

In the classic books on phase-locked loops,[1][2] published in 1966, such concepts as hold-in, pull-in, lock-in, and other frequency ranges for which PLL can achieve lock, were introduced.

They are widely used nowadays (see, e.g. contemporary engineering literature[3][4] and other publications).

Usually in engineering literature only non-strict definitions are given for these concepts.

[6][7] In the 1st edition of his well-known work, Phaselock Techniques, Floyd M. Gardner introduced a lock-in concept:[8] If, for some reason, the frequency difference between input and VCO is less than the loop bandwidth, the loop will lock up almost instantaneously without slipping cycles.

However, since even for zero frequency difference there may exist initial states of loop such that cycle slipping may take place during the acquisition process, the consideration of initial state of the loop is of utmost importance for the cycle slip analysis and, therefore, Gardner’s concept of lock-in frequency lacked rigor and required clarification.

In the 2nd edition of his book, Gardner stated: "there is no natural way to define exactly any unique lock-in frequency", and he wrote that "despite its vague reality, lock-in range is a useful concept".

for which a locked state exists is called a hold-in range, and

[6][7] Value of frequency deviation belongs to the hold-in range if the loop re-achieves locked state after small perturbations of the filter's state, the phases and frequencies of VCO and the input signals.

In addition, for a frequency deviation within the hold-in range, after a small changes in input frequency loop re-achieves a new locked state (tracking process).

[11] Assume that the loop power supply is initially switched off and then at

the power is switched on, and assume that the initial frequency difference is sufficiently large.

The loop may not lock within one beat note, but the VCO frequency will be slowly tuned toward the reference frequency (acquisition process).

The pull-in range is used to name such frequency deviations that make the acquisition process possible (see, for example, explanations in Gardner (1966, p. 40) and Best (2007, p. 61)).

Pull-in range is a largest interval of frequency deviations

[6][7][12] The difficulties of reliable numerical analysis of the pull-in range may be caused by the presence of hidden attractors in dynamical model of the circuit.

Pull-in range guarantees that PLL will eventually synchronize, however this process may take a long time.

Such long acquisition process is called cycle slipping.

If difference between initial and final phase deviation is larger than

If the loop is in a locked state, then after an abrupt change of

, the PLL acquires lock without cycle slipping.