PowerPC 400

The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage devices and supercomputers.

Applied Micro Circuits Corporation (AMCC) bought assets concerning the 400 family cores from IBM in April 2004 for $227 million, and they now market the processors under their own name.

It has a five-stage pipeline, separate 16 KB instruction and data L1 caches, a CoreConnect bus, an Auxiliary Processing Unit (APU) interface for expandability and supports clock rates exceeding 400 MHz.

It also included the CoreConnect bus technology designed to be the interface between the parts inside a PowerPC based system-on-a-chip (SoC) device.

Introduced in 2006, the 460 cores are similar to the 440 but reach 1.4 GHz, are developed with multi-core applications in mind and have 24 additional digital signal processing (DSP) instructions.

The 470 embedded and customizable core, adhering to the Power ISA v2.05 Book III-E, was designed by IBM together with LSI and implemented in the PowerPC 476FP in 2009.

[20] The 476FP core has 32/32 KB L1 cache, dual integer units and a SIMD-capable double-precision FPU that handles DSP instructions.

The 9 stage out of order, 5-issue pipeline handles speeds up to 2 GHz, supports the PLB6 bus, up to 1 MB L2 cache and up to 16 cores in SMP configurations.