Logical effort

The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit.

The stage effort is then simply: Combining these equations yields a basic equation that models the normalized delay through a single logic gate: CMOS inverters along the critical path are typically designed with a gamma equal to 2.

In other words, the pFET of the inverter is designed with twice the width (and therefore twice the capacitance) as the nFET of the inverter, in order to get roughly the same pFET resistance as nFET resistance, in order to get roughly equal pull-up current and pull-down current.

A major advantage of the method of logical effort is that it can quickly be extended to circuits composed of multiple stages.

It can be shown that in multistage logic networks, the minimum possible delay along a particular path can be achieved by designing the circuit such that the stage efforts are equal.

For a given combination of gates and a known load, B, G, and H are all fixed causing F to be fixed; hence the individual gates should be sized such that the individual stage efforts are where N is the number of stages in the circuit.