The Puma Family 16h is a low-power microarchitecture by AMD for its APUs.
It succeeds the Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h.
The Beema line of processors are aimed at low-power notebooks, and Mullins are targeting the tablet sector.
The Puma cores use the same microarchitecture as Jaguar, and inherits the design: Like Jaguar, the Puma core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.[1] AMD released a revision of the Puma microarchitecture, Puma+, which is integrated into the Carrizo-L APU platform.
APU features table