Nutshell description of a RASP: The reader will remember that the UTM is a Turing machine with a "universal" finite-state table of instructions that can interpret any well-formed "program" written on the tape as a string of Turing 5-tuples, hence its universality.
While the classical UTM model expects to find Turing 5-tuples on its tape, any program-set imaginable can be put there given that the Turing machine expects to find them—given that its finite-state table can interpret them and convert them to the desired action.
The RASP mimics this construction: it places the "program" and "data" in the holes (registers).
But unlike the UTM the RASP proceeds to "fetch" its instructions in a sequential manner, unless the conditional test sends it elsewhere.
Upon start, the state machine expects to find a number in the PC—the first "Program-Instruction" in the program (i.e. at #5).
Observe that at the end of the fetch, register #2 contains the numerical value 3 of the "operation code" ("opcode") of the first instruction JZ: Now that the number of the program-instruction (e.g. 3 = "JZ") is in register #2 -- the "Program-Instruction Register" PIR—the state machine proceeds to decrement the number until the IR is empty: If the IR were empty before decrement then the program-instruction would be 0 = HALT, and the machine would jump to its "HALT" routine.
(ib): If register #3 is not empty then the state machine can skip (ii) Second operand fetch.
It simply increments twice the PC and then unconditionally jumps back to the instruction-fetch phase, where it fetches program-instruction #8 (DEC).
The following completes the RAM's state-machine interpretation of program-instructions, INC h, DEC h and thus completes the demonstration of how a RAM can "impersonate" a RASP: Without indirect state-machine instructions INCi and DECi, to execute the INC and DEC program-instructions the state machine must use indirect copy to get the contents of the pointed-to register into spare register #3, DEC or INC it, and then use indirect copy to send it back to the pointed-to register.
239ff) An early description of this notion can be found in Goldstine-von Neumann (1946): Such an ability makes the following possible: In an influential paper Stephen A. Cook and Robert A. Reckhow define their version of a RASP: Their purpose was to compare execution-times of the various models: RAM, RASP and multi-tape Turing machine for use in the theory of complexity analysis.
The salient feature of their RASP model is no provision for indirect program-instructions (cf their discussion p. 75).
They have designed their model so each "instruction" uses two consecutive registers, one for the "operation code" (their word) and the parameter "either an address or an integer constant".