Sun designed the chip this way because server workloads usually have high re-utilization in data and instruction across processes and threads but low number of floating-point operations in general.

Thus sharing hardware resources among the four cores in a cluster leads to significant savings in area and power but low impact to performance.

[8] Nevertheless, many (arguably fine-grained) code blocks requiring synchronization could have benefited from transactional memory support of the Rock processor.

[14] The FMA feature was originally referenced to FWARC/2006/141, but this was closed and extended in FWARC/2008/455 "to successfully diagnose PCI fabric errors that occur in root domains.

[17] In February 2005, the CEO of Sun Microsystems, Scott McNealy, stated that the "taping out" of Rock would be on schedule later that year.

[23] In April 2007, Sun CEO Jonathan I. Schwartz blogged an image of a BGA-packaged Rock chip, labeled UltraSPARC RK, and disclosed that it could address 256 terabytes of virtual memory in a single system running Solaris.

[30] On 10 March 2009 Dave Dice, Yossi Lev, Mark Moir and Dan Nussbaum presented "Early Experience with a Commercial Hardware Transactional Memory Implementation" at the Fourteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '09).

They published their "experience with the hardware transactional memory (HTM) feature of two pre-production revisions of a new commercial multicore processor" in 2009.

A June 12 posting on a Sun blog announced a technical NDA-only presentation on ROCK on July 14, 2009, at the Hamburg OpenSolaris Users Group Meeting.

[42] On 15 September 2009, the paper tm_db: A Generic Debugging Library for Transactional Programs, written by Yossi Lev and Maurice Herlihy, was presented at The Eighteenth International Conference on Parallel Architectures and Compilation Techniques (PACT) Raleigh, North Carolina.

[43][44] On 26 October 2009, Dave Dice, Yossi Lev, Mark Moir and Dan Nussbaum expanded a formerly published paper "Early Experience with a Commercial Hardware Transactional Memory Implementation" which was presented at the Fourteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '09).

On 5 April 2010, Dave Dice, Yossi Lev, Virendra Marathe, Mark Moir, Marek Olszewski and Dan Nussbaum released a paper "Simplifying Concurrent Algorithms by Exploiting Hardware Transactional Memory" to be presented at the 22nd ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2010).

[46][47] On 5 April 2010, Dave Dice and Nir Shavit released a paper "TLRW: Return of the Read-Write Lock" to be presented at SPAA 2010.