StrongARM
The StrongARM is a family of computer microprocessors developed by Digital Equipment Corporation and manufactured in the late 1990s which implemented the ARM v4 instruction set architecture.
[1] It was later acquired by Intel in 1997 from DEC's own Digital Semiconductor division as part of a settlement of a lawsuit between the two companies over patent infringement.
[2] Intel then continued to manufacture it before replacing it with the StrongARM-derived ARM-based follow-up architecture called XScale in the early 2000s.
They then became interested in designs dedicated to low-power applications which led them to the ARM family.
"[3] The StrongARM was a collaborative project between DEC and Advanced RISC Machines to create a faster ARM microprocessor.
The StrongARM was designed to address the upper end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support.
Targets were devices such as newer personal digital assistants and set-top boxes.
DEC agreed to sell StrongARM to Intel as part of a lawsuit settlement in 1997.
When the semiconductor division of DEC was sold to Intel, many engineers from the Palo Alto design group moved to SiByte, a start-up company designing MIPS system-on-a-chip (SoC) products for the networking market.
[12] It was also used in a number of products including the Acorn Computers Risc PC and Eidos Optima video editing system.
The SA-110's lead designers were Daniel W. Dobberpuhl, Gregory W. Hoeppner, Liam Madden, and Richard T.
It was a scalar design that executed instructions in-order with a five-stage classic RISC pipeline.
The microprocessor was partitioned into several blocks, the IBOX, EBOX, IMMU, DMMU, BIU, WB and PLL.
The IBOX contained hardware that operated in the first two stages of the pipeline such as the program counter.
It was not designed by DEC, but was contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM) located in Neuchâtel, Switzerland.
The memory controller supported FPM and EDO DRAM, SRAM, flash, and ROM.
It was fabricated in a 0.35 μm CMOS process with three levels of aluminium interconnect and was packaged in a 208-pin TQFP.
[20][21] It was designed and manufactured in low volumes by DEC but was never put into production by Intel.
Each long-instruction word is 64 bits wide and specifies an arithmetic operation and a branch or a load/store.
The AMP communicates with the SA-110 core via an on-chip bus and it shares the data cache with the SA-110.
[23][24] It is widely used as a sense amplifier, a comparator, or just a robust latch with high sensitivity.
