Synchronous Ethernet

SyncE was standardized by the ITU-T, in cooperation with IEEE, as three recommendations: SyncE architecture minimally requires replacement of the internal clock of the Ethernet card by a phase locked loop in order to feed the Ethernet PHY.

The mechanisms needed to transport the SSM over Synchronous Ethernet are defined by the ITU-T in G.8264 in cooperation with IEEE.

The ITU-T G.8264 defines a background or heart-beat message to provide a continuous indication of the clock quality level.

However, event type messages with a new SSM quality level are generated immediately.

The synchronous signal must be filtered and regenerated by phase locked loop (PLL) at the Ethernet nodes since it degrades when passing through the network.

Duplication and security involving more than one master clock, and the existence of some kind of synchronization management protocol, are important features of modern networks.

The aim is to minimize the problems associated with signal transport, and to avoid depending on only one clock in case of failure.

This is important because if the signal crosses a legacy Ethernet island then the synchronization is lost.

Mobile Networks require a kind of synchronization
Synchronization network model for Synchronous Ethernet, SONET and SDH
Ethernet Synchronization Message Channel (ESMC) protocol data unit rec. ITU-T G.8264
Synchronization Architectures
Synchronization Network Topology
Sample of Synchronization by external reference and SSU
Timing Loop. Switch A should have remained in holdover after losing the reference