UNIVAC 1100/2200 series
This also results in four unassigned accumulators (A15+1 ... A15+4) that can only be accessed by their memory address (double word instructions on A15 do operate on A15+1).
Some were designed by Engineering Research Associates (ERA) which was later purchased and merged with the UNIVAC company.
[8] The UNIVAC 1102 or ERA 1102 was designed by Engineering Research Associates for the United States Air Force.
The UNIVAC 1104 system was a 30-bit version of the 1103 built for Westinghouse Electric, in 1957, for use on the BOMARC Missile Program.
However, by the time the BOMARC was deployed in the 1960s, a more modern computer (a version of the AN/USQ-20, designated the G-40) had replaced the UNIVAC 1104.
The machine's registers were stored in 128 words of thin-film memory, a faster form of magnetic storage.
Computer Sciences Corporation was contracted to provide a powerful optimizing Fortran IV compiler, an assembler named SLEUTH with sophisticated macro capabilities, and a very flexible linking loader.
In addition to controlling the Base Registers, it included various control "bits" that enabled the various Storage Protection features, allowed selection of either the User or Exec set of A, X & R registers, and enabled "Guard Mode" for user programs.
The 1108 CPU was, with the exception of the 128-word (200 octal) ICR (Integrated Control Register) stack, entirely implemented via discrete component logic cards, each with a 55-pin high density connector, which interfaced to a machine wire wrapped backplane.
The basic cycle time of the core memory was 750 ns, and the supporting circuitry was implemented with the same circuit card/backplane technology as the 1108 CPU.
The 1108 II, or 1108A, was the first multiprocessor machine in the series, capable of expansion to three CPUs and two IOCs (Input/Output Control Units).
Some models of the 1108 implemented the ability to divide words into four nine-bit bytes, allowing use of ASCII characters.
The IOC was a separate cabinet that contained 8 or (optionally) 16 additional I/O channels to support configurations with very large Mass Storage requirements.
A very limited number of IOCs were produced, with United Air Lines (UAL) being the primary customer.
The UAP, at its most basic level, consisted of four 1108A arithmetic units, and associated control circuitry, contained in a standalone cabinet almost identical to the 1108A CPU.
It was capable of executing a number of array-processing instructions, the most important being fast Fourier transform (FFT).
At a simplified level, one of the 1108A CPUs would move data arrays into core memory, and send the UAP an instruction packet, containing the function to be executed, and the memory address(es) of the data array(s), across a standard I/O channel.
The 1107 and early 1108 machines were aimed at the engineering/scientific computing community, so much so that the 1100 Series User Group was named the UNIVAC Scientific Exchange, or USE.
The operating systems were batch oriented, with FORTRAN and (to a much lesser extent) ALGOL being the most commonly used languages.
Instrumentation of the EXEC 8 operating system showed that, in a 1108A multiprocessor configuration, the CPU(s) were often in the "idle loop" as much as 50% of the time (see note below).
An ESC (Extended Storage Controller) was required for each pair of memory cabinets to provide the physical connection, and address translation, from the 1110 CAUs and IOAU(s).
The IOAU was completely separate, both physically and logically from the CAU, and had its own access path to the various Main and Extended Memory Modules.
Pictures/illustrations of a 1110 system typical showed the IOAU Maintenance Panel, as the CAU cabinet had no indicator lights.
[13] The major components of the 1110 system, the CAU, IOAU and Main Memory cabinets were designed using the same 55-pin high density card connectors, and machine wire wrapped backplane(s) as the 1108/1106.
Note: TTL Integrated circuits used in 1110 (1100/40) CAU, IOAU and Main Memory cabinets were ceramic 14-pin DIPs, where pins 4 and 10 were +5 volts and ground respectively: state-of-the-art in 1969.
The IOU, or Input/Output Unit was modular in design and could be configured with different Channel Modules to support varying I/O requirements.
Block Multiplexer and Byte Channel Modules allowed direct connection of high-speed disk/tape systems, and low speed printers, etc.
The Control/Maintenance Panel was now on the SIU, and provided a minimum of indicator/buttons since the system incorporated a mini-computer, based on the BC/7 (business computer) as a maintenance processor.
The CAU, IOU, and SIU units were implemented using emitter-coupled logic (ECL) on high density multi-layer PC boards.
[14] An 1100/62 Model E1 (upgraded version) – Medium Performance Multiprocessor Complex – two CPUs with 2K Buffer Storage, two IOUs with one Block Mux, and one Word Channel module (four channels), 1048K words of Main Storage, two System Support Processors, two System Consoles, and a Maintenance Console listed for $889,340.
