They are the fourth generation of UltraSPARC microprocessors, and implement the 64-bit SPARC V9 instruction set architecture (ISA).

The UltraSPARC IV was the first multi-core SPARC processor, released in March, 2004.

Instruction fetch, store bandwidth, and data prefetching were optimized.

The floating-point adder implements additional hardware to handle more not a number (NaN) and underflow cases to avoid exceptions.

The UltraSPARC IV+, released in mid-2005, is also a dual-core design, featuring enhanced processor cores and an on-chip L2 cache.