As with the SIMD instruction set extensions on other RISC processors, VIS strictly conforms to the main principle of RISC: keep the instruction set concise and efficient.
This design is very different from comparable extensions on CISC processors, such as MMX, SSE, SSE2, SSE3, SSE4, 3DNow!.
VIS re-uses existing SPARC V9 64-bit floating point registers to hold multiple 8, 16, or 32-bit integer values.
In this respect, VIS is more similar to the design of MMX than other SIMD architectures such as SSE/SSE2/AltiVec.
VIS includes a number of operations primarily for graphics support, so most of them are only for integers.