Two stages of MPU-based translation are provided to enable multiple operating systems to be isolated from one another under the control of a hypervisor.

[1] However, many real-time operating systems (RTOS), with an emphasis on total control, have traditionally regarded the lack of an MMU as a feature, not a bug.

Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog).

This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc.

To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.