It has an enhanced instruction set and a 16-bit stack pointer, as well as several new electrical signals for improved system hardware management.

Thereafter, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software.

In 1981, Bill Mensch, founder and CEO of WDC, began development of the 65C02 with his production partners, primarily Rockwell Semiconductor and Synertek.

The result was the 65C816, finished in March 1984, with samples provided to both Apple and Atari in the second half of the year and full release in 1985.

[5] Mensch was aided during the design process by his sister Kathryn, who was responsible for part of the device's layout.

Both were produced on the same fabrication lines and diverged only during the last metalization stages when the chip was being connected to the external pins.

In the 1990s, both the 65C816 and 65C02 were converted to a fully static core, which made it possible to completely stop the processor's Ø2 clock without loss of register contents.

This feature, along with the use of asynchronous static RAM, made it possible to produce designs that used minimal power when in a standby state.

As of April 2024[update], the W65C816S is available from WDC in 40 pin PDIP, PLCC44, or 44-pin TQFP packaging, as an MCU through the W65C265,[8] and as IP cores for ASIC integration[9][10] (for example Winbond's W55V9x series of TV Edutainment ICs[11]).

The CPU automatically enters emulation mode when it is powered on or reset, which allows it to replace a 65(C)02, assuming one makes the required circuit changes to accommodate the different pin layout.

As the accumulator and index register sizes are independently settable, it is possible, for example, to have the accumulator set to eight bits and the index registers set to 16 bits, giving the programmer the ability to manipulate individual bytes over a 64KB range without having to perform pointer arithmetic.

[14] During an opcode or operand fetch cycle, PB is prepended to the program counter (PC) to form the 24-bit effective address.

This processor characteristic makes it possible to sanely execute 6502 or 65c02 code that uses 16-bit addresses to reference data elements.

Unlike PB, DB can be changed under program control, something that might be done to access data beyond the limits of 16-bit addressing.

In native mode, the 65c816 can relocate direct (zero) page anywhere in bank $00 (the first 64 KB of memory) by writing the 16-bit starting address into DP.

The m and x bits in SR determine how the user registers (accumulator and index) appear to the rest of the system.

If the m bit in SR is cleared, the B-accumulator will be "ganged" to the A-accumulator to form a 16-bit register (called the C-accumulator).

The exceptions are the instructions that transfer the direct page register (DP) and stack pointer (SP) to/from the accumulator.