As serial-based PCI Express devices become less active, it is possible for the computer's power management system to take the opportunity to reduce overall power consumption by placing the link PHY into a low-power mode and instructing other devices on the link to follow suit.
While ASPM brings a reduction in power consumption, it can also result in increased latency as the serial bus needs to be 'woken up' from low-power mode, possibly reconfigured and the host-to-device link re-established.
This is known as ASPM exit latency and takes up valuable time which can be annoying to the end user if it is too obvious when it occurs.
L0s concerns setting low power mode for one direction of the serial link only, usually downstream of the PHY controller.
L1 shuts off PCI Express link completely, including the reference clock signal, until a dedicated signal (CLKREQ#) is asserted, and results in greater power reductions though with the penalty of greater exit latency.