ARM big.LITTLE

The intention is to create a multi-core processor that can adjust better to dynamic computing needs and use less power than clock scaling alone.

For example, it might use a smaller (fewer transistors) memory cache, or a simpler microarchitecture such as removing out-of-order execution.

Another is that the CPUs no longer have equivalent abilities, and matching the right software task to the right CPU becomes more difficult.

There are three ways[6] for the different processor cores to be arranged in a big.LITTLE design, depending on the scheduler implemented in the kernel.

The most powerful use model of big.LITTLE architecture is heterogeneous multi-processing (HMP), which enables the use of all physical cores at the same time.

[12] The paired arrangement allows for switching to be done transparently to the operating system using the existing dynamic voltage and frequency scaling (DVFS) facility.

It poses unique problems for the kernel scheduler, which, at least with modern commodity hardware, has been able to assume all cores in a SMP system are equal rather than heterogeneous.

The technology also offers more fine grained per core voltage control and faster L2 cache speeds.

However, DynamIQ is incompatible with previous ARM designs and is initially only supported by the Cortex-A75 and Cortex-A55 CPU cores and their successors.