William Kahan, primary architect of the original IEEE 754 floating-point standard noted, "For now the 10-byte Extended format is a tolerable compromise between the value of extra-precise arithmetic and the price of implementing it to run fast; very soon two more bytes of precision will become tolerable, and ultimately a 16-byte format ... That kind of gradual evolution towards wider precision was already in view when IEEE Standard 754 for Floating-Point Arithmetic was framed.
A common software technique to implement nearly quadruple precision using pairs of double-precision values is sometimes called double-double arithmetic.
A similar technique can be used to produce a double-quad arithmetic, which is represented as a sum of two quadruple-precision values.
A separate question is the extent to which quadruple-precision types are directly incorporated into computer programming languages.
The procedure call standard for the ARM 64-bit architecture (AArch64) specifies that long double corresponds to the IEEE 754 quadruple-precision format.
[21] Even if long double is not quadruple precision, however, some C/C++ compilers provide a nonstandard quadruple-precision type as an extension.
For example, gcc provides a quadruple-precision type called __float128 for x86, x86-64 and Itanium CPUs,[22] and on PowerPC as IEEE 128-bit floating-point using the -mfloat128-hardware or -mfloat128 options;[23] and some versions of Intel's C/C++ compiler for x86 and x86-64 supply a nonstandard quadruple-precision type called _Quad.
[27] IEEE quadruple precision was added to the IBM System/390 G5 in 1998,[32] and is supported in hardware in subsequent z/Architecture processors.
The Siemens 7.700 and 7.500 series mainframes and their successors support the same floating-point formats and instructions as the IBM System/360 and System/370.
The VAX processor implemented non-IEEE quadruple-precision floating point as its "H Floating-point" format.
The NEC Vector Engine architecture supports adding, subtracting, multiplying and comparing 128-bit binary IEEE 754 quadruple-precision numbers.
[41] The RISC-V architecture specifies a "Q" (quad-precision) extension for 128-bit binary IEEE 754-2008 floating-point arithmetic.