Bus analyzer

It also helps in later phases of a product life cycle, in examining communication interoperability between systems and between components, and clarifying hardware support concerns.

It is essentially a logic analyzer with some additional knowledge of the underlying bus traffic characteristics.

These devices are typically connected in series between the host computer and the target drive, where they 'snoop' traffic on the bus, capture it and present it in human-readable format.

Such exercisers can emulate partial or full communication stacks which comply with the specific bus communication standard, thus allowing engineers to surgically control and generate bus traffic to test, debug and validate their designs.

Exercisers are usually used in conjunction with analyzers, so the engineer gets full visibility of the communication data captured on the bus.