Intel Core (microarchitecture)

It is a major evolution over the Yonah, the previous iteration of the P6 microarchitecture series which started in 1995 with Pentium Pro.

[3] Intel had been developing Merom, the 64-bit evolution of the Pentium M, since 2001,[2] and decided to expand it to all market segments, replacing NetBurst in desktop computers and servers.

It inherited from Pentium M the choice of a short and efficient pipeline, delivering superior performance despite not reaching the high clocks of NetBurst.

[a] The first processors that used this architecture were code-named 'Merom', 'Conroe', and 'Woodcrest'; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations.

While the Core microarchitecture is a major architectural revision, it is based in part on the Pentium M processor family designed by Intel Israel.

The new architecture is a dual core design with a shared L2 cache engineered for maximum performance per watt and improved scalability.

For most Woodcrest CPUs, the front-side bus (FSB) runs at 1333 MT/s; however, this is scaled down to 1066 MT/s for lower end 1.60 and 1.86 GHz variants.

[citation needed] Previously, Intel announced that it would now focus on power efficiency, rather than raw performance.

It is used only in ultra-low voltage Core 2 Solo U2xxx and in Celeron processors and is identified as CPUID family 6 model 22.

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23.

In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order.

Stepping L2 and M0 are the Allendale chips with just 2 MB L2 cache, reducing production cost and power consumption for low-end processors.

The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MB L2 cache further reducing the power consumption and manufacturing cost for the low-end.

Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache and six instead of the usual two cores, which leads to an unusually large die size of 503 mm2.

BIOS updates were gradually being released to provide support for the Penryn technology, and the QX9775 is only compatible with the Intel D5400XS motherboard.

This is because all Conroe-based processors require a new power delivery feature set specified in Voltage Regulator-Down (VRD) 11.0.

This requirement is a result of Conroe's significantly lower power consumption, compared to the Pentium 4/D CPUs it replaced.

While DDR2 memory models with tighter timing specifications do improve performance, the difference in real world games and applications is often negligible.

Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the translation lookaside buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data.

Among those who have stated the errata to be particularly serious are OpenBSD's Theo de Raadt[22] and DragonFly BSD's Matthew Dillon.