Typically, inputs of a circuit module will indicate their readiness to receive, which will be "acknowledged" by the connected output by sending data (encoded in such a way that the receiver can detect the validity directly[1]), and once that data has been safely received, the receiver will explicitly acknowledge it, allowing the sender to remove the data, thus completing the handshake, and allowing another datum to be transmitted.
In a delay-insensitive circuit, there is therefore no need to provide a clock signal to determine a starting time for a computation.
Instead, the arrival of data to the input of a sub-circuit triggers the computation to start.
The main advantage of such circuits is their ability to optimize processing of activities that can take arbitrary periods of time depending on the data or requested function.
The Delay-Insensitive (DI) class is the most robust of all asynchronous circuit delay models.