Quasi-delay-insensitive circuit

Developed in response to the performance challenges of building sub-micron, multi-core architectures with conventional synchronous designs, QDI circuits exhibit lower power consumption, extremely fine-grain pipelining, high circuit robustness against process–voltage–temperature variations, on-demand (event-driven) operation, and data-dependent completion time.

Advantages Disadvantages QDI circuits have been used to manufacture a large number of research chips, a small selection of which follows.

The correct operation of a QDI circuit requires that events be limited to monotonic digital transitions.

Instability (glitch) or interference (short) can force the system into illegal states causing incorrect/unstable results, deadlock, and circuit damage.

For a QDI circuit, there are a few exceptions in which the stability property is maintained using timing assumptions guaranteed with layout constraints rather than causality.

Martin also established that it is impossible to design useful systems without including at least some isochronic forks given reasonable assumptions about the available circuit elements.

The half-cycle timing assumption assumes that the driver and feedback will stabilize before the inputs to the logic are allowed to switch.

[timing 4] This allows the designer use the output of the logic directly, bypassing the driver and making shorter cycles for higher frequency processing.

It represents a timing assumption as a virtual causality arc to complete a broken cycle in the event graph.

This allows designers to reason about timing assumptions as a method to realize circuits with higher throughput and energy efficiency by systematically sacrificing robustness.

[synthesis 2] Hand-shaking expansions are a subset of CHP in which channel protocols are expanded into guards and assignments and only dataless operators are permitted.

A petri net (PN) is a bipartite graph of places and transitions used as a model for QDI circuits.

Event-rule systems (ER) use a similar notation to implement a restricted subset of petri net functionality in which there are transitions and arcs, but no places.

The goal of these transformations is to convert the original sequential program into a parallel set of communicating process which each map well to a single pipeline stage.

The possible transformations include: Once the program is decomposed into a set of small communicating processes, it is expanded into hand-shaking expansions (HSE).

[synthesis 2] The production rules are not necessarily CMOS implementable at this point, so bubble reshuffling moves signal inversions around the circuit in an attempt to make it so.

[synthesis 7] Synthesizing a QDI circuit using this method strictly implements the control flow as dictated by the program.

Unlike Steven Burns' approach using circuit templates, Tangram mapped the syntax to a strict set of standard cells, facilitating layout as well as synthesis.

Weak condition half buffer (WCHB) is the simplest and fastest of the logic families with a 10 transition pipeline cycle (or 6 using the half-cycle timing assumption).

More complex computations can generally be broken up into simpler stages or handled directly with one of the pre-charge families.

Pre-charge half buffer (PCHB) uses domino logic to implement a more complex computational pipeline stage.

This removes the long pull-up network problem, but also introduces an isochronic fork on the input data which must be resolved later in the cycle.