Delay-locked loop

From the outside, a DLL can be seen as a negative delay gate placed in the clock path of a digital circuit.

A DLL compares the phase of its last output with the input clock to generate an error signal which is then integrated and fed back as the control to all of the delay elements.

In the Control Systems jargon, the DLL is a loop one step lower in order and in type with respect to the PLL, because it lacks the 1/s factor in the controlled block: the delay line has a transfer function phase-out/phase-in that is just a constant, the VCO transfer function is instead GVCO/s.

It may be further remarked that, in the case where the integrator instead of the flat gain is chosen, the PLL that can be obtained is unstable.

The phase shift can be specified either in absolute terms (in delay chain gate units), or as a proportion of the clock period, or both.

The delay locked loop is a variable delay line whose delay is locked to the duration of the period of a reference clock.
Depending on the signal processing element in the loop (a flat amplifier or an integrator),
the DLL loop can be of 0th order type 0 or of 1st order type 1.