Design rule checking

For example, an enclosure rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin, by a metal layer.

[1] Many other such rules exist and are explained in detail in the documentation provided by the semiconductor manufacturer.

Design rule sets have become increasingly more complex with each subsequent generation of semiconductor process.

To meet this goal of improving die yields, DRC has evolved from simple measurement and Boolean checks, to more involved rules that modify existing features, insert new features, and check the entire design for process limitations such as layer density.

DRC software usually takes as input a layout in the GDSII standard format and a list of rules specific to the semiconductor process chosen for fabrication.

Carefully "stretching" or waiving certain design rules is often used to increase performance and component density at the expense of yield.

[4] Usually DRC checks will be run on each sub-section of the ASIC to minimize the number of errors that are detected at the top level.

With today's processing power, full-chip DRC's may run in much shorter times as quick as one hour depending on the chip complexity and size.