EPROM

EPROMs are easily recognizable by the transparent fused quartz (or on later models' resin) window on the top of the package, through which the silicon chip is visible, and which permits exposure to ultraviolet light during erasing.

[3] Development of the EPROM memory cell started with investigation of faulty integrated circuits where the gate connections of transistors had broken.

[5] In 1967, Dawon Kahng and Simon Min Sze at Bell Labs proposed that the floating gate of a MOSFET could be used for the cell of a reprogrammable ROM (read-only memory).

This creates an avalanche discharge of electrons, which have enough energy to pass through the insulating oxide layer and accumulate on the gate electrode.

[7] Because of the high insulation value of the silicon oxide surrounding the gate, the stored charge cannot readily leak away and the data can be retained for decades.

Photons of the UV light cause ionization within the silicon oxide, which allows the stored charge on the floating gate to dissipate.

The process takes several minutes for UV lamps of convenient sizes; sunlight would erase a chip in weeks, and indoor fluorescent lighting over several years.

The erasing window must be kept covered with an opaque label to prevent accidental erasure by the UV found in sunlight or camera flashes.

This method of erasure allows complete testing and correction of a complex memory array before the package is finally sealed.

Once the package is sealed, information can still be erased by exposing it to X radiation in excess of 5*104 rads,[a] a dose which is easily attained with commercial X-ray generators.

Because higher-density parts have little exposed oxide between the layers of interconnects and gate, ultraviolet erasing becomes less practical for very large memories.

However, these require many weeks lead time to make, since the artwork or design in an IC mask layer or photomask must be altered to store data on the ROMs.

[14][15] The second generation 2704/2708 devices switched to n-MOS technology and to three-rail VCC = +5 V, VBB = -5 V, VDD = +12 V power supply with VPP = 12 V and a +25 V pulse in Programming mode.

The n-MOS technology evolution introduced single-rail VCC = +5 V power supply and single VPP = +25 V[16] programming voltage without pulse in the third generation.

However, as this was not universal, programmer software also would allow manual setting of the manufacturer and device type of the chip to ensure proper programming.