With Advanced Performance Extensions, the Extended EVEX prefix redefines the semantics of several payload bits.
The following features are carried over from the VEX scheme: EVEX also extends VEX with additional capabilities: For example, the EVEX encoding scheme allows conditional vector addition in the form of where {k1} modifier next to the destination operand encodes the use of opmask register k1 for conditional processing and updates to destination, and {z} modifier (encoded by EVEX.z) provides the two types of masking (merging and zeroing), with merging as default when no modifier is attached.
Base-plus-index and scale-plus-index addressing require the SIB byte, which encodes 2-bit scale factor as well as 3-bit index and 3-bit base registers.
To accommodate this, VEX has IS4 addressing mode, which encodes 4th operand (a vector register) in bits Imm8[7:4] of the immediate constant.
Intel Advanced Performance Extensions introduce several new variants of the 3-byte payload in the EVEX prefix, which are used to encode Extended GPR registers R16-R31 and new conditional instructions.