To deliver these capabilities, the F100 was implemented using bipolar junction transistors, as opposed to the metal oxide semiconductor (MOS) process used by most other processors of the era.
They followed this with several other commercial designs, most notably the Ferranti Atlas of 1962, for a time the fastest computer in the world.
[1] As part of the deal with ICT, Ferranti were barred from sales into the commercial computer market.
[a] In typical designs, the bipolar layout also required three or four extra masking steps, each of which was time-consuming and increased the possibility of the chip being damaged during processing.
However, the MOS system was more sensitive to impurities in the semiconductor feedstock, which led to electrical noise that reduced performance and also limited its operating conditions.
This process, originally developed at Bell Labs, produced a dramatically simplified bipolar gate which required fewer masking steps and was only slightly larger than the equivalent MOS.
This was of little interest to either Bell or Fairchild, who were happy with their MOS processes, and neither had developed the system beyond experimental production runs.
[4] Ferranti invested heavily in the CDI process, working to raise the operating voltage from 3 to 5V for compatibility with their existing transistor-transistor logic (TTL) devices that were already widely used in military applications.
Convinced that the microprocessor represented a strategic change in military applications, in 1974 the UK Ministry of Defence agreed to sponsor an effort by Ferranti to produce a military-grade microprocessor design using the CDI process, whose high power-handling allowed them to operate in electrically noisy environments.
[4] Based on studies of the economics of chip fabrication, Ferranti concluded that they had a budget of about 1,000 gates before the design would be too expensive.
To produce a 16-bit design with this limited gate count, the arithmetic logic unit (ALU) used a bit-serial architecture.
This slows the performance of mathematical operations, so that the minimum time needed to complete an instruction is 36 clock cycles.
This performance hit is offset somewhat by the 8 MHz clock speed, roughly double that of the fastest MOS-based CPUs of the era.
To accomplish this, the data and address lines share pins, and thus require multiple cycles to complete the reading of a single instruction.
[3] For comparison, the Texas Instruments TMS9900, another 16-bit design introduced the same year, had double the gate count and was packaged in an expensive custom 64-pin DIP.
[6] While this made it uncompetitive with MOS-based commercial processors like the $25 Zilog Z80 or $11 MOS 6502 in the same 100-unit lots, it was very competitive with other military-spec designs like the Z80's military-rated unit at $165.
Desiring to make more sales into the United States, the company began looking for an established US military supplier they could buy and use as the basis for their own division in the country.
A lengthy court process ensued, and the debt load of the purchase along with the cost of the litigation drove Ferranti into bankruptcy in December 1993.
Among the few are a display F100-L chip at the Museum of Science and Industry in Manchester, also there are two types of display F100-L chips and a DATA book at The ICL Computer Museum, and a small number of cards from a F100 microcomputer at the Centre for Computing History.
[6] At the time the F100 was designed, memory was extremely expensive and typical machines of the era generally featured only 4 kB of SRAM, so the missing 16th bit in the address was not an important consideration.
The 16-bit ACC (accumulator) and OR (operand register) are used to hold values being manipulated by the arithmetic logic unit (ALU) during calculations and comparisons.
[9] The CR contained a set of seven bits:[9] The F100 had a total of four addressing modes; direct, immediate, pointer and immediate indirect.
Immediate mode was similar to direct, but the value to be accessed is placed in the 16-bits following the instruction in order to allow larger constants.
This was used for bitwise comparisons; the instructions included which bit to be tested as the first operand, the location in memory as the second, and the address to jump to as the third.
For instance, ADD and SUB had alternate versions, ADS and SBS, which performed the operation and then stored the result back into the operand address.