[4] The processor contains 16 PCI Express generation 3 lanes[1] to connect to accelerators (hypothetical e.g. GPUs and FPGAs).
The processor also integrates a TofuD fabric controller with 10 ports implemented as 20 lanes of high-speed 28 Gbit/s to connect multiple nodes in a cluster.
[8] Fujitsu intends to produce lower specification machines with reduced assistant cores.
[2][3] Reliability, availability and serviceability (RAS) capabilities are claimed, i.e. ~128,400 error checkers in total.
[11][12] The Isambard 2 supercomputer is being built for a consortium in the United Kingdom, led by the University of Bristol and also including the Met Office, using the Fujitsu processors.