SPARC64 is a microprocessor developed by HAL Computer Systems and fabricated by Fujitsu.
The SPARC64 is a superscalar microprocessor that issues four instructions per cycle and executes them out of order.
The CPU die contains the majority of logic, all of the execution units and a level 0 (L0) instruction cache.
The L0 instruction cache has a capacity of 4 KB, is direct-mapped and has a one-cycle latency.
The MMU die contains the memory management unit, cache controller and the external interfaces.
The data cache is protected by error correcting code (ECC) and parity.
The SPARC64 II has higher performance due to higher clock frequencies enabled by the new process and circuit tweaks; and a higher instructions per cycle (IPC) count due to the following microarchitecture improvements: It was fabricated by Fujitsu in their CS-60 process, a 0.35 μm, five-layer metal CMOS process.
[4] The main competitors were the HP PA-8500, IBM POWER3 and Sun UltraSPARC II.
Numerous modifications and improvements were made to the microarchitecture, such as the replacement of the MMU and a new system interface using the Ultra Port Architecture.
The complex SPARC64 II memory management unit (MMU) was replaced with a simpler one that is compatible with the Solaris operating system.
Previously, SPARC64 systems ran SPARC64/OS, a derivative of Solaris developed by HAL that supported the SPARC64.
The associated performance loss was mitigated by the provision of a large external L2 cache with a capacity of 1 to 16 MB.
The L2 cache is accessed with a dedicated 128-bit data bus that operates at the same or half clock frequency of the microprocessor.
The SPARC64 II's proprietary system interface was replaced by one compatible with the Ultra Port Architecture.
The system bus operates at half, a third, quarter or fifth the frequency of the microprocessor, up to a maximum of 150 MHz.
The Ultra Port Architecture (UPA) signals are compatible with 3.3 V Low Voltage Transistor Transistor Logic (LVTTL) levels with the exception of differential clock signals which are compatible with 3.3 V pseudo emitter coupled logic (PECL) levels.
It had larger L1 instruction and data caches, doubled in capacity to 128 KB each; better branch prediction as the result of a larger BHT consisting of 16,384 entries; support for the Visual Instruction Set (VIS); and a L2 cache built from double data rate (DDR) SRAM.
[5] It was fabricated by Fujitsu in their 0.15 μm CS85 process with six levels of copper interconnect.