It describes the definitions of logic values to be used in electronic design automation, for the VHDL hardware description language.
[2] It was sponsored by the Design Automation Standards Committee of the Institute of Electrical and Electronics Engineers (IEEE).
The primary data type std_ulogic (standard unresolved logic) consists of nine character literals (see table on the right).
[1] This system promoted a useful set of logic values that typical CMOS logic designs could implement in the vast majority of modeling situations, including: In VHDL, the hardware designer makes the declarations visible via the following library and use statements: Many hardware description language (HDL) simulation tools, such as Verilog and VHDL, support an unknown value like that shown above during simulation of digital electronics.
HDL synthesis tools usually produce circuits that operate only on binary logic.
"Don't care"s are especially common in state machine design and Karnaugh map simplification.