Advanced Programmable Interrupt Controller

As its name suggests, the APIC is more advanced than Intel's 8259 Programmable Interrupt Controller (PIC), particularly enabling the construction of multiprocessor systems.

It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems.

The 82489DX enabled construction of symmetric multiprocessor (SMP) systems with the Intel 486 and early Pentium processors; for example, the reference two-way 486 SMP system used three 82489DX chips, two as local APICs and one as I/O APIC.

[3] Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system.

The Message Signaled Interrupts (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.

Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.

[9] Another advantage of the local APIC is that it also provides a high-resolution (on the order of one microsecond or better) timer that can be used in both interval and one-off mode.

[15] According to a 2009 Intel benchmark using Linux, the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced the latency even more, by a factor of nearly seven relative to the XT-PIC baseline.

[17] The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.

The improved interface reduces the number of needed APIC register accesses for sending inter-processor interrupts (IPIs).

[18][19] APICv is Intel's brand name for hardware virtualization support aimed at reducing interrupt overhead in guests.

[20][21] AMD announced a similar technology called AVIC,[22][23] it is available family 15h models 6Xh (Carrizo) processors and newer.

IBM however developed their MultiProcessor Interrupt Controller (MPIC) based on the OpenPIC register specifications.

[28] MPIC was used in PowerPC based designs, including those of IBM, for instance in some RS/6000 systems,[29] but also by Apple, as late as their Power Mac G5s.