A SHA instruction set is a set of extensions to the x86 and ARM instruction set architecture which support hardware acceleration of Secure Hash Algorithm (SHA) family.
[1] Instructions for SHA-512 was introduced in Arrow Lake and Lunar Lake in 2024.
The original SSE-based extensions added four instructions supporting SHA-1 and three for SHA-256.
The newer SHA-512 instruction set comprises AVX-based versions of the original SHA instruction set marked with a V prefix and these three new AVX-based instructions for SHA-512: All recent AMD processors support the original SHA instruction set: The following Intel processors support the original SHA instruction set: The following Intel processors will support the newer SHA-512 instruction set: This microcomputer- or microprocessor-related article is a stub.
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