Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for error correction code (ECC) memory, higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture (MCA).

They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE).

[6] Xeon D is targeted towards microserver and edge computing markets with lower power consumption and integrated I/O blocks such as network interface controllers.

Xeon D was introduced to compete with emerging ARM hyperscale server solutions that offered greater multi-threaded performance and power effiency.

Some shortcomings that make Xeon processors unsuitable for most consumer-grade desktop PCs include lower clock rates at the same price point (since servers run more tasks in parallel than desktops, core counts are more important than clock rates), and, usually, the lack of an integrated graphics processing unit (GPU).

The first-generation Xeon Phi is a completely different type of device more comparable to a graphics card; it is designed for a PCI Express slot and is meant to be used as a multi-core coprocessor, like the Nvidia Tesla.

The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.

Later experience with the 130 nm process allowed Intel to create the Xeon MP branded Gallatin with 4 MB cache.

A slightly updated core called "Irwindale" was released in early 2005, with 2 MB L2 cache and the ability to have its clock speed reduced during low processor demand.

The first dual-core CPU branded Xeon, codenamed Paxville DP, product code 80551, was released by Intel on October 10, 2005.

The only Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a 90 nm process.

[12] On May 23, 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed Dempsey (product code 80555).

On March 14, 2006, Intel released a dual-core processor codenamed Sossaman and branded as Xeon LV (low-voltage).

However, this was abandoned in favor of low-voltage versions of the Woodcrest LV processor leaving the Sossaman at a dead-end with no upgrade path.

Intel claimed that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the 5000 series Dempsey.

On November 11, 2007, Intel released the dual-core CPU (Xeon branded 5200 series) codenamed Wolfdale-DP (product code 80573).

[19][20][21][22] Intel released rebranded versions of its quad-core (2×2) Core 2 Quad processor as the Xeon 3200-series (product code 80562) on January 7, 2007.

Intel released relabeled versions of its quad-core Core 2 Quad Yorkfield Q9300, Q9400, Q9x50 and QX9770 processors as the Xeon 3300-series (product code 80569).

[32][33] The 7300 series, codenamed Tigerton QC (product code 80565) is a four-socket (packaged in Socket 604) and more capable quad-core processor, consisting of two dual core Core 2 architecture silicon chips on a single ceramic module, similar to Intel's Xeon 5300 series Clovertown processor modules.

Bloomfield (or Nehalem-E) is the codename for the successor to the Xeon 3300 series, is based on the Nehalem microarchitecture and uses the same 45 nm manufacturing methods as Intel's Penryn.

Gulftown and Westmere-EP, six-core 32 nm architecture Westmere-based processors, are the basis for the Xeon 36xx and 56xx series and the Core i7-980X.

[41] Most models limit the number of cores and QPI links as well as the L3 cache size in order to get a broader range of products out of the single chip design.

Starting with Westmere-EX, the naming scheme has changed once again, with "E7-xxxx" now signifying the high-end line of Xeon processors using a package that supports larger than two-CPU configurations, formerly the 7xxx series.

The Xeon E3-12xx line of processors, introduced in April 2011, uses the Sandy Bridge chips that are also the base for the Core i3/i5/i7-2xxx and Celeron/Pentium Gxxx products using the same LGA 1155 socket, but with a different set of features disabled.

Xeon E3-12xx v2 is a minor update of the Sandy Bridge-based E3-12xx, using the 22 nm shrink, and providing slightly better performance while remaining backwards compatible.

Some of the main benefits of this generation, compared to the previous one, are improved power efficiency, higher core counts, and bigger last level caches (LLCs).

One of the new features of this generation is that Xeon E5 v3 models with more than 10 cores support cluster on die (COD) operation mode, allowing CPU's multiple columns of cores and LLC slices to be logically divided into what is presented as two non-uniform memory access (NUMA) CPUs to the operating system.

By keeping data and instructions local to the "partition" of CPU which is processing them, thus decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications.

Following the usual SKU nomenclature, Xeon E7-48xx v3 and E7-88xx v3 series allow multi-socket operation, supporting up to quad- and eight-socket configurations, respectively.

As before, the main difference between the desktop and server versions is added support for ECC memory and improved energy efficiency in the Xeon-branded parts.