Intel iPSC

[1] The iPSC used a Hypercube internetwork topology of connections between the processors internally inspired by the Caltech Cosmic Cube research project.

[3] Each node had a 80286 CPU with 80287 math coprocessor, 512K of RAM, and eight Ethernet ports (seven for the hypercube interconnect, and one to talk to the cube manager).

[1] A message passing interface called NX that was developed by Paul Pierce evolved throughout the life of the iPSC line.

It was available in several configurations, the base setup being one cabinet with 16 Intel 80386 processors at 16 MHz, each with 4 MB of memory and a 80387 coprocessor on the same module.

[12] The base modules could be upgraded to the SX (Scalar eXtension) version by adding a Weitek 1167 floating point unit.

Having multiple cabinets as part of the same iPSC/2 system is necessary to run the maximum number of nodes and allow them to connect to VX modules.

[22][23] The iPSC/860 was also the original development platform for the Tachyon parallel ray tracing engine[24][25] that became part of the SPEC MPI 2007 benchmark, and is still widely used today.

[26] The iPSC line was superseded by a research project called the Touchstone Delta at the California Institute of Technology which evolved into the Intel Paragon.