Many of the techniques of CPU and OS design that improve interrupt latency will decrease throughput and increase processor utilization.
Lastly, trying to reduce processor utilization may increase interrupt latency and decrease throughput.
The Intel APIC architecture is well known for producing a huge amount of interrupt latency jitter.
An RTOS makes the promise that no more than a specified maximum amount of time will pass between executions of subroutines.
For example, most network cards implement transmit and receive ring buffers, interrupt rate limiting, and hardware flow control.