Within the field of electronics Level-sensitive scan design (LSSD) is part of an integrated circuit manufacturing test process.
It is a DFT scan design method which uses separate system and scan clocks to distinguish between normal and test mode.
Latches are used in pairs, each has a normal data input, data output and clock for system operation.
For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held low during system operation but cause the scan data to be latched when pulsed high during scan.
Allowing it to be used as a second system latch reduces the silicon overhead.