The many cores in the Xeon Phi processors, along with their associated vector processing units, enable them to consume many more gigabytes per second than traditional DRAM DIMMs can supply.
Its physical placement on the processor imposes some limits on capacity – up to 16 GB at launch, although speculated to go higher in the future.
The memory can be partitioned at boot time, with some used as cache for more distant DDR, and the remainder mapped into the physical address space.
The application can request pages of virtual memory to be assigned to either the distant DDR directly, to the portion of DDR that is cached by the MCDRAM, or to the portion of the MCDRAM that is not being used as cache.
[3] When used as cache, the latency of a miss accessing both the MCDRAM and DDR is slightly higher than going directly to DDR, and so applications may need to be tuned[4] to avoid excessive cache misses.