Master-checker or master/checker is a hardware-supported fault tolerance architecture for multiprocessor systems, in which two processors, referred to as the master and checker, calculate the same functions in parallel in order to increase the probability that the result is exact.
[1] A recurrence of discrepancies between the two processors could indicate a flaw in the software, hardware problems, or timing issues between the clock, CPUs, and/or system memory.
Depending on the merit of a correct answer, a checker-CPU may or may not be warranted.
In order to alleviate some of the cost in these situations, the checker-CPU may be used to calculate something else in the same algorithm, increasing the speed and processing output of the CPU system.
[citation needed] This microcomputer- or microprocessor-related article is a stub.