Media-independent interface
As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC).
The original MII design has been extended to support reduced signals and increased speeds.
[further explanation needed] The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network.
The transmit enable signal is held high during frame transmission and low when the transmitter is idle.
The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode.
MDC and MDIO constitute a synchronous serial data interface similar to I²C.
As with I²C, the interface is a multidrop bus so MDC and MDIO can be shared among multiple PHYs.
This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.
The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in 10 Mbit/s mode.
There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree.
Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u.
Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex.
The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC.
However, the IEEE version of the related MII standard specifies 68 Ω trace impedance.
[citation needed] National also suggests that traces be kept under 0.15 m long and matched within 0.05 m on length to minimize skew.
The interface operates at speeds up to 1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or 100 Mbit/s.
For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this.
This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink.
The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to 2.5 Gbit/s.
QSGMII predates NBASE-T and is used to connect multi-port PHYs to MACs, for example in network routers.
[10] The PSGMII (penta serial gigabit media-independent interface) uses the same signal lines as QSGMII, but operates at 6.25 Gbit/s, which supports five 1 gigabit/s ports through one MII.
XGMII features two 32-bit datapaths (Rx & Tx) and two four-bit control flows (Rxc and Txc), operating at 156.25 MHz DDR (312.5 MT/s).
