In particular, MSI allows the device to write a small amount of interrupt-describing data to a special memory-mapped I/O address, and the chipset then delivers the corresponding interrupt to a processor.
[1][2][3] A common misconception with MSI is that it allows the device to send data to a processor as part of the interrupt.
On the mechanical side, fewer pins makes for a simpler, cheaper, and more reliable connector.
The interrupt could arrive before the DMA write was complete, and the processor could read stale data from memory.
[5] To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished.
[6] PCI defines two optional extensions to support Message Signalled Interrupts, MSI and MSI-X.
In particular, it made it difficult to target individual interrupts to different processors, which is helpful in some high-speed networking applications.
MSI-X allows a larger number of interrupts and gives each one a separate target address and data word.
[12] According to a 2009 Intel benchmark using Linux, using MSI reduced the latency of interrupts by a factor of almost three when compared to I/O APIC delivery.
[13] In the Microsoft family of operating systems, Windows Vista and later versions have support for both MSI and MSI-X.
[15] Solaris Express 6/05 released in 2005 added support for MSI an MSI-X as part of their new device driver interface (DDI) interrupt framework.