PCI configuration space
A single PCI expansion card can respond as a device and must implement at least function number zero.
The Cache Line Size register must be programmed before the device is told it can use the memory-write-and-invalidate transaction.
This should normally match the CPU's cache line size, but the correct setting is system dependent.
The Subsystem Vendor ID–Subsystem ID combination identifies the card, which is the kind of information the driver may use to apply a minor card-specific change in its operation.
The system's firmware (e.g. BIOS) or the operating system program the Base Address Registers (commonly called BARs) to inform the device of its resources configuration by writing configuration commands to the PCI controller.
When the computer is powered on, the PCI bus(es) and device(s) must be enumerated by BIOS or operating system.
Bus enumeration is performed by attempting to access the PCI configuration space registers for each buses, devices and functions.
If no response is received from the device's function #0, the bus master performs an abort and returns an all-bits-on value (FFFFFFFF in hexadecimal), which is an invalid VID/DID value, thus the BIOS or operating system can tell that the specified combination bus/device_number/function (B/D/F) is not present.
When a read to a specified B/D/F combination for the vendor ID register succeeds, the system firmware or operating system knows that it exists; it writes all ones to its BARs and reads back the device's requested memory size in an encoded form.
Upon power-off, these settings are lost and the procedure is repeated next time the system is powered back on.
Since this entire process is fully automated, the user is spared the task of configuring any newly added hardware manually by changing DIP switches on the cards themselves.
This automatic device discovery and address space assignment is how plug and play is implemented.
[5] Classically, BARs were limited to a size of 256MB, but modern graphics cards have framebuffers much larger than that.
To reduce electrically loading down the timing critical (and thus electrically loading sensitive) AD[] bus, the IDSEL signal on the PCI slot connector is usually connected to its assigned AD[n+11] pin through a resistor.
This causes the PCI's IDSEL signal to reach its active condition more slowly than other PCI bus signals (due to the RC time constant of both the resistor and the IDSEL pin's input capacitance).
Thus Configuration Space accesses are performed more slowly to allow time for the IDSEL signal to reach a valid level.
The scanning on the bus is performed on the Intel platform by accessing two defined standardized ports.
[6] The legacy method was present in the original PCI, and it is called Configuration Access Mechanism (CAM).
The section of the addressable space is "stolen" so that the accesses from the CPU don't go to memory but rather reach a given device in the PCI Express fabric.
