The instructions are usually programmed into the Flash memory of the processor, and automatically executed by the microcontroller on startup.
PICmicro chips have a Harvard architecture and instruction words have unusual sizes.
Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations.
Most are simply general-purpose storage (RAM), while some locations are reserved for special function registers.
(The other exceptions, which are not memory-mapped, are the return address stack, and the tri-state registers used to configure the GPIO pins.)
Memory operands are specified by absolute address; the location is fixed at compile time.
Models with more registers (special function registers plus RAM) than fit into the instruction provide multiple banks of memory, and use one of two mechanisms for accessing them: PIC processors with more than 256 words of program use paged memory.
Any operation which does not specify the full destination address (such as a 9-bit GOTO or an 8-bit write to the PCL register) fills in the additional high bits from the corresponding part of PCLATH.
These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack.
The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 128 registers and 2048 words of code to be directly addressed.
ELAN Microelectronics Corp. make a series of PICmicro-like microcontrollers with a 13-bit instruction word.
The accumulator is called ACC rather than W, and the destination is specified by a suffix to the instruction mnemonic rather than an operand.
Two-operand instructions by default write to the accumulator, and use an M suffix to indicate a memory destination.)
[18][19][20] Although clearly derived from the Microchip PIC12 series,[18][21] there are some significant differences: The 14-, 15- and 16-bit instruction sets primarily differ in having wider address fields, although some encoding changes are made to allow a few additional instructions (such as CNEQSN, which performs a compare and skip if not equal.)
[1] Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture.
The 8-bit f field determines the address in combination with the a bit and the 4-bit bank select register (BSR).
If a=0, the BSR is ignored and the f field is sign-extended to the range 0x000–0x07F (global RAM) or 0xF80–0xFFF (special function registers).
The PIC18 extends the FSR/INDF mechanism used in previous PICmicro processors for indirect addressing in two ways: First, it provides three file select registers.
Hycon Technology make a series of microcontrollers (part number prefixes HY10 through HY17) with an "H08" CPU core which is very similar to the PIC18.
There are numerous mnemonic changes (for example, an unconditional relative branch is called BRA by Microchip but JR by Hycon), and a small number of functional changes:[29] There is also a reduced H08B variant.
In 2001, Microchip introduced the dsPIC series of chips,[37] which entered mass production in late 2004.